module GCD(
  input         clock,
  input         reset,
  input  [15:0] io_a,
  input  [15:0] io_b,
  input         io_load,
  output [15:0] io_out,
  output        io_valid
);
  reg [15:0] x; 
  reg [15:0] y; 
  wire [15:0] _T_2 = x - y; 
  wire [15:0] _T_5 = y - x; 
  assign io_out = x; 
  assign io_valid = y == 16'h0; 
  always @(posedge clock) begin
    if (io_load) begin 
      x <= io_a; 
    end else if (x > y) begin 
      x <= _T_2; 
    end
    if (io_load) begin 
      y <= io_b; 
    end else if (!(x > y)) begin 
      if (x <= y) begin 
        y <= _T_5; 
      end
    end
  end
endmodule
